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october 2010 doc id 17962 rev 1 1/32 AN3275 application note improving the performance of smartcard interfaces using the st8024l introduction the st8024l is a smartcard interface offered as a drop-in replacement for the st8024 device. enhancements and changes to the st8024l device include: improved performance by reducing the noise sensitivity in the charge pump incorporated 1.8 v v cc output lower v th threshold voltage this application note provides information and suggestions for the optimal use and performance of the st8024l smartcard interface, including pcb layout, external component placement, and connections (see st8024l application hardware guidelines on page 18 ). the implementation of all the blocks and procedures for card activation and deactivation (see figure 1 ) of the smartcard are also explained. the st8024l is a smartcard interface designed to minimize microprocessor hardware and software complexity in all applications that require a smartcard (e.g., set-top box, electronic payment, pay tv, and identification cards). the electrical characteristics of the st8024l are in accordance with new digital systems (nds) and compliant with iso7816-3, gsm11.11, and emv 4.0. two devices (st8024lcdr and st8024 lctr) in the st8024l family have been certified by nds. figure 1. st8024l internal block diagram c s 1 8 100 s t 8 024l c1? c1+ 1 8 poradj/1. 8 v s equencer o s cillator clock circuitry clk hor s eq thermal protection clock buffer i/o tran s ceiver i/o tran s ceiver i/o tran s ceiver r s t buffer v cc generator internal o s cillator 2.5 mhz s tep-up converter alarm power_on en1 clkup en2 pv cc en5 en4 en 3 voltage s en s e internal reference s upply 21 6 7 5 100nf 100nf v ddp 100nf v dd 2 3 20 19 3 1 2 clkdiv2 (2) clkdiv2 (1) 5v/ 3 v cmdvcc r s tin off v dd v re f r 2 ( 1) r 1 (1) xtal1 xtal2 (2) 24 25 27 2 8 26 22 aux1uc (2) aux2uc (2) i/ouc gnd 4 8 v up pgnd 100nf v cc 100nf cgnd r s t clk pre s pre s (2) aux1 (2) aux2 (2) i/o 17 14 16 15 10 9 1 3 12 11 www.st.com
contents AN3275 2/32 doc id 17962 rev 1 contents 1 activation/deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 card clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 emergency deactivation/fault detection . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 poradj v dd undervoltage without external resistor bridge . . . . . . . . . . . 9 3.2 poradj v dd undervoltage with external divider . . . . . . . . . . . . . . . . . . . 11 3.3 fault on card removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 v cc short-circuit fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 v ddp drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 overtemperature fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 st8024l application hardware gui delines . . . . . . . . . . . . . . . . . . . . . . 18 4.1 power supply optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 clock section optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 smartcard connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 input and output connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AN3275 list of tables doc id 17962 rev 1 3/32 list of tables table 1. clk division factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. resistor values for v th(ext)fall trip point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. v poradj trip point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. v cc selection settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
list of figures AN3275 4/32 doc id 17962 rev 1 list of figures figure 1. st8024l internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. st8024l activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. card activation/deactivation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. clkdiv change clock duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6. st8024l automatic deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. external resistor bridge applied to poradj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. v th(ext) rise (external rising th reshold voltage on v dd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. v th(ext) fall (external falling threshold on v dd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. card extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 11. st8024l activation sequence (after t debounce ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 12. st8024l current supply sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 13. i sc short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 14. deactivation caused by v ddp drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15. st8024l application pcb top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 16. st8024l application pcb bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 17. step-up converter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 18. st8024l application pcb storage and pumping capacitors . . . . . . . . . . . . . . . . . . . . . . . 22 figure 19. st8024l application pcb crystal (xtal) connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 20. st8024l application pcb smartcard connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 21. ripple on v cc output voltage, 80 ma pulsed load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 22. ripple on v cc output voltage, 65 ma pulsed load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 23. ripple on v cc output voltage, 50 ma pulsed load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 24. st8024l application pcb schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AN3275 activation/deactivation sequence doc id 17962 rev 1 5/32 1 activation/deactivation sequence the core of the st8024l is the sequencer (shown in figure 1 on page 1 ) that must coordinate the enable signals for the activation and deactivation sequence as well as check for possible fault conditions. the smart card is basically a microcontroller and needs to be activated/deactivated by a correct sequence as required by the iso/iec7816 standard. the st8024l activation and deactivation sequences are shown in figure 2 and figure 3 on page 6 , respectively. please refer to the st8024l datasheet for details. figure 2 shows the activation sequence (the card is active) and cmdvcc taken from high to low. the activation sequence starts and the first block to be enabled is the step-up converter (v up ), linked to en1 (see figure 1 ), while the last enabled signal is rst that allows the card software to start. figure 3 shows the deactivation sequence (when cmdvcc goes high). the circuit executes an automatic deactivation sequence, finishing in the inactive state after t de (deactivation time). figure 2. st8024l activation sequence
activation/deactivation sequence AN3275 6/32 doc id 17962 rev 1 figure 3. deactivation sequence
AN3275 activation/deactivation sequence doc id 17962 rev 1 7/32 figure 4. card activation/deactivation flowchart s t a rt end error me ssa ge ?no c a rd? off pin = v dd s et cmdvcc from high to low initi a te a ctiv a tion ch a rge p u mp i s on reg u l a tor i s on i/o i s en ab led clk i s a ctive s et r s tin from low to high s t a rt c a rd comm u nic a tion completed s et cmdvcc from low to high initi a te de a ctiv a tion r s t goe s low clk i s di sab led i/o i s di sab led reg u l a tor i s off ch a rge p u mp i s off end f au lt detection off pin = gnd no no ye s al a rm error me ssa ge ?error d u ring comm u nic a tion? initi a te de a ctiv a tion r s t goe s high clk i s di sab led i/o i s di sab led reg u l a tor i s off ch a rge p u mp i s off s et cmdvcc from low to high end no a l a rm am0494 3 v1
card clock AN3275 8/32 doc id 17962 rev 1 2 card clock the card clock signal (clk) is present on th e clk pin when the st8024l is activated. it is linked to the internal en4 signal (see figure 1 on page 1 ) and its frequency is obtained according to the settings in ta b l e 1 . according to the iso/iec7816 specifications, the clk duty cycle must be guaranteed between 45% and 55%, even when the status of clkdiv1 or clkdiv2 changes. figure 5 shows how the st8024l ensures duty cycle accuracy by waiting for completion of a whole clock cycle before changing the frequency (clkdiv1 change, rising edge of ch2). the output duty cycle is 50% 5%, even if the clock division changes. the card clock signal (clk) can be established by connecting a crystal (?xtal ? ) between the xtal1 and xtal2 pins, or by an external signal applied to the xtal1 pin. in this case, the xtal2 pin must be left floating. the external sign al voltage level must be limited between gnd and v dd voltage. figure 5. clkdiv change clock duty cycle ch1 = output clk waveform ch2 = clkdiv1 pin conditions: v dd = 3.3 v; v ddp = 5 v; 5/3v = h mode: active f xtal = 10 mhz; clkdiv2 = 0 v table 1. clk division factor clkdiv1 clkdiv2 f clk 0 0 1/8 f xtal 0 1 1/4 f xtal 1 1 1/2 f xtal 10f xtal
AN3275 emergency deactivation/fault detection doc id 17962 rev 1 9/32 3 emergency deactivation/fault detection st8024l is equipped with a fault detection circ uitry which monitors the following conditions (see figure 1 on page 1 ): v dd undervoltage fault on card removal v cc short-circuit v ddp drop, and overtemperature 3.1 poradj v dd undervoltage without ex ternal resistor bridge the poradj pin can be used to provide early detection of power failure on v dd . the st8024l logic circuitry is supplied by v dd . in order to avoid voltage spikes that could cause damage or malfunction of the device and/or card, a voltage supervisor block is embedded (see figure 1 ). this block monitors v dd and when it gets lower than v th2 (falling threshold voltage on v dd , 2.45 v, typ), the supervisor immediat ely starts the deactivation sequence and v cc goes low. as v dd goes higher than v th2 + v hys2 , (v hys2 is the hysteresis of threshold voltage, 100 mv, typ), after a certain amount of time (t w + t debounce , where t w is the internal power-on reset pulse width, 8 ms typ, see figure 6 on page 10 ), cmdvcc goes low. the activation sequence starts and v cc goes high. the poradj pin can be left floating, but connecting it to gnd to avoid capturing noise is recommended. note: see fault on card removal on page 14 for t debounce feature details.
emergency deactivation/fault detection AN3275 10/32 doc id 17962 rev 1 figure 6. st8024l automatic deactivation sequence ch1 = cmdvcc ch2 = v cc ch3 = off ch4 = v dd conditions: v dd = 3.3 v; v ddp = 5 v; 5/3v = h mode: active f xtal = 10 mhz; clkdiv2 = 0 v note: deactivation: v th2 2.393 v. activation: as v dd v th2 + v hys2 ( 2.498 v) and cmdvcc goes low, v cc goes high.
AN3275 emergency deactivation/fault detection doc id 17962 rev 1 11/32 3.2 poradj v dd undervoltage with external divider in this case, a resistor bridge is applied to the poradj pin (see figure 7 ). v th(ext) rise and v th(ext) fall are the external rising threshold voltage and the external falling threshold voltage on v dd , respectively. they are the voltages on pin poradj that switch the device on and off. by knowing these values and using the formula: v poradj =(r 2 /r 1 + r 2 ) x v dd it is possible to set r 1 and r 2 such that the device powers on and off at the values of v dd desired by the user (r 1 + r 2 = 100 k typ). in particular, r 1 and r 2 have to be set so that, when v dd is getting low, before turning the microcontroller off, the smartcard has to be switched off properly as well. the same is true for the microcontroller startup in that the smartcard has to be turned on after the microcontroller. figure 8 and figure 9 on page 13 show the v th(ext) rise and v th(ext) fall on the poradj pin (1.196 v and 1.155 v, respectively). the v th(ext)fall threshold of the st8024l is slightly lower (80 mv typ.) than the st8024 device. if for example, the microcontroller is shut down at 2.5 v, appropriate resistor values must be chosen to ensure proper deactivation of the st8024l device. ta bl e 2 shows an example of the resistor values between the st8024 and st8024l devices if the microcontroller is shut down at 2.5 v. table 2. resistor values for v th(ext)fall trip point st8024 st8024l r1 50 k 55.5 k r2 50 k 44.5 k v th(ext)fall 1.25 v 1.14 v table 3. v poradj trip point v dd v poradj st8024 st8024l 5.0 2.500 2.275 4.5 2.250 2.048 4.0 2.000 1.820 3.5 1.750 1.593 3.0 1.500 1.365 2.5 1.250 1.138 2.0 1.000 0.910
emergency deactivation/fault detection AN3275 12/32 doc id 17962 rev 1 as long as v dd gets the proper startup value (so that v th(ext) rise = 1.196 v), off goes low for t w + t debounce (t w 16 ms, in this case). during this time, the device cannot be turned on by cmdvcc . to turn the device on, cmdvcc must go low for at least approximately 16 ms (while off is high). figure 7. external resistor bridge applied to poradj figure 8. v th(ext) rise (external rising threshold voltage on v dd ) ch1 = cmdvcc ch2 = v cc ch3 = off ch4 = v th(ext) rise v dd gnd r1 to poradj r2 ai11 88 5
AN3275 emergency deactivation/fault detection doc id 17962 rev 1 13/32 figure 9. v th(ext) fall (external falling threshold on v dd ) ch1 = cmdvcc ch2 = v cc ch3 = off ch4 = v th(ext) fall note: when v th(ext) fall = 1.155 v, the device starts switching off and v cc goes low.
emergency deactivation/fault detection AN3275 14/32 doc id 17962 rev 1 3.3 fault on card removal if the smartcard is pulled out from its socket (pres goes high or pres goes low), the deactivation sequence starts. the off pin goes low and the device switches off (see figure 10 ). in order to avoid bouncing on the pres (or pres) signal at card insertion or extraction, as the card is inserted again, off goes high just after a period t debounce ( 8 ms). if cmdvcc goes low before this time, after card inse rtion, it will not init iate the activation. cmdvcc must wait for t debounce before toggling from high to low to initiate the activation. figure 11 on page 14 shows the start of the activation sequence after t debounce has elapsed. figure 10. card extraction figure 11. st8024l activation sequence (after t debounce )
AN3275 emergency deactivation/fault detection doc id 17962 rev 1 15/32 3.4 v cc short-circuit fault protection the st8024l is able to supply the card with current pulses of about 140 ma for no longer than 5.5 s, typical (see figure 12 and figure 13 on page 16 ). short-circuit protection is an important interface feature that warns the sequencer block if the output current is higher than the short-circuit current limit ( 120 ma) for too long. this characteristic allows the device to supply the card with current pulses higher than the maximum allowed, if their duration is not too long. if the current pulses last for more than 5.5 s, the deactivation sequence starts to protect the card. the off pin goes low so as to warn the microcontroller about the overcurrent fault. the sequence in figure 13 on page 16 shows how the current pulse becomes long enoug h to activate the short-circuit protection. figure 12. st8024l current supply sequence ch1 = cmdvcc ch2 = i sc pulse ch3 = v cc ch4 = off
emergency deactivation/fault detection AN3275 16/32 doc id 17962 rev 1 figure 13. i sc short-circuit protection
AN3275 emergency deactivation/fault detection doc id 17962 rev 1 17/32 3.5 v ddp drop the voltage supervisor also monitors the drop in v ddp . when v ddp falls below the minimum threshold (see figure 14 ), the deactivation sequence starts. the off pin goes low and v cc goes off. figure 14. deactivation caused by v ddp drop ch1 = v ddp ch2 = cmdvcc ch3 = v cc ch4 = off 3.6 overtemperature fault protection overtemperature protection is another important interface feature that warns the sequencer block of fault events. if the temperature is higher than the shutdown temperature (150 c, typ), the deactivation sequence starts to protect the card. the off pin goes low so as to warn the microcontroller about the overtemperature fault.
st8024l application hardware guidelines AN3275 18/32 doc id 17962 rev 1 4 st8024l application hardware guidelines this section contains some optimization gu idelines concerning pcb layout as well as external component placement and connections. the referenced application board in figure 15 and figure 16 on page 19 has two layers and uses these guidelines to meet nds application requirements (refer to figure 24 on page 29 ). the pcb layout provides completely separate supply and gnd copper planes, which allow each plan to act as a shield for each group of noise-sensitive device pins. the pgnd, and cgnd and gnd planes share a common point on the bottom layer of the pcb (see top, figure 16 on page 19 ). figure 15. st8024l application pcb top layer
AN3275 st8024l application hardware guidelines doc id 17962 rev 1 19/32 figure 16. st8024l application pcb bottom layer
st8024l application hardware guidelines AN3275 20/32 doc id 17962 rev 1 4.1 power supply optimization the st8024l devices support three smartcard v cc voltages: 1.8 v, 3.0 v and 5.0 v. the st8024lcdr and st8024lctr only support 3.0 v and 5.0 v v cc . the v cc selection is controlled by the supply voltage selector pin 5v/3v (pin 3) as shown in figure 1 on page 1 . if the 5v/3v pin is connected to v dd , the v cc voltage is 5 v and v cc is 3 v if 5v/3v pin is connected to gnd. the st8024lacdr and st8024ltr support all 3 supply card voltages and are available in the so-28 and tssop-20 packages. the v cc selection is controlled by the supply voltage selector pins 5v/3v (pin 3) and 1.8v (pin 18). the 1.8 v signal has priority over the 5v/3v pin. when the 1.8v pin is connected to v dd , the v cc voltage is 1.8 v and it overrides any setting on the 5v/3v pin. when the 1.8v pin is connected to gnd, the 5v/3v pin selects the 5 v or 3 v v cc . a step-up converter supplied by v ddp is used for the v cc voltage generation. it doubles the input voltage v ddp or follows it, depending on the 5/3v and v ddp values: 5/3v = h and v ddp > 5.8 v; voltage follower 5/3v = h and v ddp < 5.7 v; voltage doubler 5/3v = l and v ddp > 4.1 v; voltage follower 5/3v = l and v ddp < 4.0 v; voltage doubler the c1? and c1+ pins are used for duplicating the supply voltage v ddp by using the 100 nf pumping capacitor (c4). the charge pump output pin (v up ) has to be connected to a 100 nf storage capacitor (c5) to stabilize the voltage. table 4. v cc selection settings 5v/3v 1.8v pin v cc output 003 v 105 v x 1 1.8 v
AN3275 st8024l application hardware guidelines doc id 17962 rev 1 21/32 figure 17. step-up converter block diagram on/off pgnd 100nf 100nf c1? 7 17 l 65 100nf v up v cc v cc regulator pv cc en2 st8024l output step-up mode selector c1+ am04942v1
st8024l application hardware guidelines AN3275 22/32 doc id 17962 rev 1 a small amount of noise is introduced into the design because of the switching circuitry. in order to reduce it and improve the efficiency of the step-up converter, the capacitors must be connected as closely as possible to the pins (see figure 18 ). an equivalent series resistance (esr) < 350 m at 100 khz is recommended. the evaluation board is equipped with murata grm31m7u1h104ja01b capacitors. however, other capacitors with an esr of up to 350 m at 100 khz are sufficient to work within the specifications. figure 18. st8024l application pcb storage and pumping capacitors
AN3275 st8024l application hardware guidelines doc id 17962 rev 1 23/32 4.2 clock section optimization recommendations for the pcb design clock area include: the xtal should be connected as closely as possible to the xtal pins to reduce signal reflections, especially for high frequency applications (see figure 19 ). two compensation capacitors (c9 and c10), each 15 pf (typ) can improve the oscillator startup performance. even without th ese additional capacitors the clk duty cycle is guaranteed between 45% and 55% (according to the nds specifications), with frequencies up to 26 mhz. figure 19. st8024l application pcb crystal (xtal) connection
st8024l application hardware guidelines AN3275 24/32 doc id 17962 rev 1 4.3 smartcard connections in typical applications, a 100 nf filter capacitor (c3) is connected to the v cc output towards gnd/cgnd, near the st8024l pins. a second 10 0 nf capacitor (c8) is connected between the card socket pins c1 (v cc ) and c5 (cgnd), near the card slot (see figure 20 ). in order to reduce noise and avoid coupling effects, the wire length between the st8024l and card should be as short as possible. another recommendation is to keep the clk track far away from the other signal tracks to limit coupling with the transceiver lines. further decoupling is gained if the clock track is shielded by a gnd/cgnd plane or track on the pcb. keeping the pgnd and gnd/cgnd planes as large as possible improves power supply noise rejection. with this in mind, the board design should connect these planes with a large number of vias between the top and bottom board layers (3-4 vias per cm 2 ). the st8024l has been enhanced to reduce the noise sensitivity in the charge pump and to improve the performance of the device. the v cc spikes are much lower than 350 mv pp even when a pulsed load of up to 80 ma is applied with v cc = 5 v, up to 65 ma with v cc = 3 v and up to 50 ma with v cc = 1.8 v. figure 21 on page 26 shows a typical v cc output waveform where an 80 ma pulsed load is applied and the measured ripple is lower than 95 mv. with a 65 ma pulsed load applied, the measured ripple is less than 65 mv, and when a 50ma pulsed load is applied, the measured ripple is less than 55 mv.
AN3275 st8024l application hardware guidelines doc id 17962 rev 1 25/32 figure 20. st8024l application pcb smartcard connections
st8024l application hardware guidelines AN3275 26/32 doc id 17962 rev 1 figure 21. ripple on v cc output voltage, 80 ma pulsed load v dd = 3.3 v v ddp = 5.5 v ch1 = ripple on v cc output voltage ch2 = 80 ma pulsed current i cc
AN3275 st8024l application hardware guidelines doc id 17962 rev 1 27/32 figure 22. ripple on v cc output voltage, 65 ma pulsed load v dd = 3.3 v v ddp = 5.5 v ch1 = ripple on v cc output voltage ch2 = 65 ma pulsed current i cc
st8024l application hardware guidelines AN3275 28/32 doc id 17962 rev 1 figure 23. ripple on v cc output voltage, 50 ma pulsed load v dd = 3.3 v v ddp = 5.5 v ch1 = ripple on v cc output voltage ch2 = 50 ma pulsed current i cc
AN3275 st8024l application hardware guidelines doc id 17962 rev 1 29/32 figure 24. st8024l application pcb schematic ai11 8 9 8 1 2 3 4 6 5 a b c d 6 5 4 3 2 1 d c b a st8024l smartcard connector cgnd aux1 aux2 i/o pres k2 k1 aux2 i/o nc gnd clk c3 c6 c4 c5 c2 j7 vcc vdd j3 gnd j2 t.p. card k 2.7v - 6.5v 4v 6.5v rstin cmdvcc vthsel ?off c8 100nf c1 100nf c10 y1 10mhz 10pf c9 10pf 47f 100nf 100nf 100nf c12 330nf 100nf rst vcc poradj aux1 clk rst vcc rstin vdd gnd off xtal1 xtal2 i/ouc aux1uc aux2uc 24 25 26 27 28 19 20 21 22 15 16 17 18 4 3 2 1 3 2 1 23 5 4 3 2 1 10 9 8 7 14 13 12 11 8 7 10 9 6 5 6 vup s1 vddp s2 gndp clkdiv2 clkdiv1 u2 u1 pres cmdvcc 5v/3v 3 2 1 3 2 1 3 2 1 clkdiv1 aux2uc aux1uc i/ouc 3 2 1 3 2 1 3 2 1 3 2 1 clkdiv2 3 2 1 5/3v 3 2 1 pres config (jp17) please connect the 2 jumpers as follows: no switch +pres (sw n.c.) ?pres (sw n.o.) j1 pins j2 pins 1 - 5 2 - 5 pin 2 of jp17 to j8 2 - 3 1 - 4 pres conf. and sw kind j8 gnd-pres vddp j1 10k r6 + c7 47f + jp17 pres 3 4 5 2 1 n.c. or n.o. switch is included in the smartcard connector. please select jp17 as specified in the pres configuration.
st8024l application hardware guidelines AN3275 30/32 doc id 17962 rev 1 4.4 input and output connections the three data lines of the smartcard signals are pulled high via an 11 k resistor through v cc and the three data lines of the microcontroller signals i/ouc, aux1uc and aux2uc are pulled high via an 11 k resistor through v dd , thus allowing operation when v cc is not equal to v dd . the device and the microcontroller must use the same v dd supply. pins clkdiv1, clkdiv2, rstin, pres, i/ouc, aux1uc, aux2uc, 5v/3v , 1.8v, cmdvcc and off are referenced to v dd . if the xtal1 pin is to be driven by an external clock, also reference this pin to v dd . it is recommended that no control smartcard signals are to be shared with any other devices. sharing could result in inadvertent activation or deactivation of the smartcard.
AN3275 revision history doc id 17962 rev 1 31/32 5 revision history table 5. document revision history date revision changes 04-oct-2010 1 initial release.
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